1. Field of the Invention
The present invention relates to a display device and, more particularly, to a liquid crystal display (LCD) device and a fabrication method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for a driving circuit-integrated LCD device in which an amorphous silicon thin film transistor and a polycrystalline silicon thin film transistor are simultaneously formed within a single panel.
2. Description of the Related Art
In the information society, importance of a display device for use a visual information transfer medium is increasing. In order for a display device to have value in the market, the display device should have the characteristics of low power consumption, a thin profile, light weight and high picture quality. A liquid crystal display (LCD) is a flat panel display that has these characteristics as well as being suitable for mass production, so various types of brand-new products of LCDs have been introduced into the market. LCDs are now seen as a replacement for the existing cathode ray tubes (CRTs).
In general, the LCD device displays a desired image by controlling light transmittance of liquid crystal cells by separately supplying a data signal according to image information to the liquid crystal cells arranged in a matrix form. The LCD device includes a color filter substrate, or a first substrate, an array substrate, or a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate. On the array substrate, a thin film transistor (TFT) is commonly used as a switching device, and an amorphous silicon thin film or a polycrystalline silicon thin film may be used as a channel layer of the TFT.
In fabricating the LCD device, a plurality of masking processes (namely, a photolithography process) are required to fabricate the LCD device, including the TFT. Reducing the number of masking processes increases productivity. Further, reducing the number of masking processes decreases the probabilities in mask alignment error. The structure of a related art LCD device will now be described with reference to FIG. 1.
FIG. 1 is a perspective view of a related art LCD device. As shown in FIG. 1, the related art LCD device includes a color filter substrate 5, an array substrate 10 and a liquid crystal layer 40 formed between the color filter substrate 5 and the array substrate 10. The color filter substrate 5 includes a color filter (C) having red (R), green (G) and blue (B) sub-color filters 7, a black matrix 6 separating the sub-color filters (C) for blocking light transmitted through the liquid crystal layer 40, and a transparent common electrode 8 for applying a voltage to the liquid crystal layer 40. On the array substrate 10, gate lines 16 are arranged horizontally and data lines 17 are arranged vertically to define pixel regions (P). A thin film transistor (TFT), a switching device, is formed adjacent to the crossing of one of the gate lines 16 and one of the data lines 17, and a pixel electrode 18 is formed in each pixel region (P). The pixel region (P) is a sub-pixel corresponding to a single sub-color filter 7, and a color image is obtained by combining the three types of red, green and blue colors. The red, green and blue sub-pixels make one pixel, and the TFT (T) is connected to the red, green and blue sub-pixels.
Although not shown in FIG. 1, the TFT (T) includes a gate electrode connected to the gate line 16, a source electrode connected to the data line 17, and a drain electrode connected to the pixel electrode 18. In addition, the TFT (T) includes an insulation film for insulating the gate electrode from the source electrode, drain electrode and a channel layer. The channel layer forms a conductive channel between the source and drain electrodes in response to a signal on the gate electrode.
The channel layer is formed of an amorphous silicon thin film or a polycrystalline silicon thin film. A polycrystalline silicon TFT using polycrystalline silicon thin film has a different structure from that of the amorphous silicon TFT. Thus, the polycrystalline silicon TFT and the amorphous silicon TFT are formed separately through different fabrication process when both a polycrystalline silicon TFT and an amorphous silicon TFT are formed on the same substrate.
Depending on where the source, drain and gate electrodes are positioned with respect to each other, a TFT can have either a staggered structure or a coplanar structure. FIGS. 2A and 2B are cross-sectional views of a related art amorphous silicon TFT with the staggered structure and a related art polycrystalline silicon TFT with the coplanar structure, respectively. With reference to FIG. 2A, the staggered structure is formed such that a gate electrode 21′ is formed on a lower layer and source and drain electrodes 22′ and 23′ are formed on an upper layers with an insulation film 15 interposed therebetween. The staggered structure is typically used for amorphous silicon TFTs. As shown in FIG. 2B, the coplanar structure is formed such that a gate electrode 21″ is formed on the gate insulating film 15A and source and drain electrodes 22″ and 23″ are formed through the gate insulating film 15A and on the passivation layer 15B. The coplanar is typically used for a CMOS (Complementary Metal Oxide Semiconductor) polycrystalline silicon TFT. The amorphous silicon TFT with the staggered structure is formed directly on the substrate 10 as shown in FIG. 2A. The polycrystalline silicon TFT with the coplanar structure is formed on a buffer layer 11 on the array substrate, as shown in FIG. 2B. layer.
In the case of the amorphous silicon TFT with the staggered structure, the gate insulation film 15, an active pattern 24′ and an ohmic-contact layer 25 are formed through successive deposition, so that interface states are minimized. In the case of forming channel etch (BCE) as shown in FIG. 2A, an over-etching margin of the silicon thin film should be provided. Thus, a deposited amorphous silicon thin film needs to have the thickness of about 170 nm.
In the case of the polycrystalline silicon TFT with the coplanar structure shown in FIG. 2B, the amorphous silicon thin film is crystallized to form an active pattern 24″ and then a gate electrode 21″ is formed. This results in degradation of the interface characteristics as compared with the amorphous silicon TFT. The thickness of the silicon thin film required for enhancing crystallization efficiency is about 50 nm, which is relatively thin compared to the amorphous silicon TFT.
The two TFT structures are independent structures, so it is difficult to implement both structures within a single panel due to the problems of designing, masking and a fabrication process with the current level of technologies. To fabricate a driving circuit-integrated LCD device in which both a driving circuit part and a pixel part are installed on the glass substrate, the polycrystalline silicon TFT, which is suitable for a high speed operation of 1 MHz or higher and has relatively large mobility should be used in the driving circuit part. Thus, in the related art driving circuit-integrated LCD device, a pixel driving TFT for driving each pixel of the pixel part and a driving circuit TFT for operating the pixel driving TFT and applying signals to the gate line and the data line are fabricated with amorphous silicon. In this case, the TFT of the driving circuit part requires an additional thermal process to form the polycrystalline silicon thin film and is fabricated by using a different fabrication process from that of the amorphous silicon TFT for the pixel part.
The polycrystalline silicon thin film is formed by thermally processing the amorphous silicon thin film after the amorphous silicon thin film is formed. High-priced equipment, such as laser, is required for the thermal processing of the amorphous silicon thin film into a polycrystalline silicon thin film. Such thermal processing can take a long time. In addition, since the polycrystalline silicon TFT has the coplanar structure, different from the stagger structure of the amorphous silicon TFT, the existing fabrication line used for the amorphous silicon TFT cannot be used for a polycrystalline silicon TFT.